The present invention relates to a decoder circuit for a semiconductor memory device, which comprises a combination of a high level selection circuit and a low level selection circuit so as to attain the requirements of low power consumption and high speed operation.
In the prior art, there are mainly three types of decoder circuits, i.e., a decoder circuit constructed by a high level selection circuit (hereinafter referred to as an H decoder), a decoder circuit constructed by a low level selection circuit (hereinafter referred to as an L decoder), and a decoder circuit constructed of two stages of high level selection circuits (hereinafter referred to as a two-stage H decoder). The H decoder has an advantage of simplified gate circuits, but consumes a relatively large amount of electric power in comparison with other types of decoders because, when one of the outputs of the decoder is to be selected, the other outputs must be grounded by conducting currents through elements connected between the other outputs and the ground. The L decoder has an advantage of relatively low power consumption in comparison with the other types of decoders because, when one of the outputs of the decoder is to be selected, only that one output must be grounded. However, the L decoder has a disadvantage of a limited number of input gates because of its circuit structure.
As a two-stage H decoder, Japanese Patent Application No. 50-84820 (Japanese Patent Laid-Open No. 52-8739) discloses, as hereinafter described in detail, a system which utilizes emitter coupled logic (ECL) and a diode (or a mutli-emitter) matrix, and which selects or does not select the diode matrix in a two-dimensional manner or higher dimensional manner, in order to reduce the consumption of electric power and to reduce the number of elements in the decoder circuit.
The decoder circuit mentioned above is advantageous with regard to reduced power consumption and reduced number of elements as compared with the conventional decoder circuit, but presents the defect that the output waveform has a distortion because of low driving capacity of the high level selection circuit. Therefore, when the reading level is higher than a point at which the output waveform rises slowly, the access time tends to be delayed. Further, in the above mentioned decoder circuit, although power consumption is reduced by employing the emitter coupled logic ECL and a diode (or a multi-emitter) matrix, it is still desirable to reduce the power consumption in a decoder circuit.